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cywb0124ab cywb0125ab west bridge ? antioch? usb/mass storage peripheral controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-07978 rev. *m revised november 20, 2013 west bridge ? antioch? usb/mass storage peripheral controller features slim ? architecture, enabling simultaneous and independent data paths between processor and usb, and between usb and mass storage high speed usb at 480 mbps ? usb-2.0 compliant ? integrated usb 2.0 transceiver, smart serial interface engine ? 16 programmable endpoints mass storage device support ? mmc/mmc+/sd/ce-ata ? nand flash: x8 or x16, slc ? full nand management (ecc, wear leveling) memory mapped interface to main processor dma slave support supports microsoft ? media transfer protocol (mtp) with optimized data throughput ultra low power, 1.8 v core operation low power modes small footprint, 6 6 mm vf bga, and less than 4 4 mm wlcsp selectable clock input frequencies ? 19.2 mhz, 24 mhz, 26 mhz, and 48 mhz applications cellular phones portable media players personal digital assistants digital cameras portable video recorder west bridge antioch processor interface mass storage interface control registers 8051 mcu high-speed usb 2.0 xcvr u p s sd/mmc+/ce-ata nand slim tm logic block diagram
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 2 of 31 contents functional overview ........................................................ 3 slim? architecture .................................................... 3 turbo-mtp support ..... .............. .............. ........... ......... 3 8051 microprocessor ... .............. .............. ........... ......... 3 configuration and status registers ............................. 3 processor interface (p-port) ........................................ 3 usb interface (u-port) ................................................ 3 mass storage support (s-port) ............ .............. ......... 3 clocking ....................................................................... 4 power domains ........................................................... 5 power modes .............................................................. 5 antioch in wlcsp ....................................................... 6 absolute maximum ratings .......................................... 12 operating conditions ..................................................... 12 dc characteristics ......................................................... 12 usb transceiver ....................................................... 14 capacitance .................................................................... 14 ac test loads and waveforms ..................................... 14 ac characteristics ......................................................... 15 usb transceiver ....................................................... 15 p-port interface ......................................................... 15 sd/mmc parameters ................................................ 23 reset and standby timing parameters .................... 24 ordering information ...................................................... 25 ordering code definitions ..... .................................... 25 package diagrams .......................................................... 26 acronyms ........................................................................ 27 document conventions ................................................. 27 units of measure ....................................................... 27 document history page ................................................. 28 sales, solutions, and legal information ...................... 31 worldwide sales and design s upport ......... .............. 31 products .................................................................... 31 psoc? solutions ...................................................... 31 cypress developer community ................................. 31 technical support ................. .................................... 31
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 3 of 31 functional overview slim ? architecture the simultaneous link to independent multimedia (slim) architecture allows three differ ent interfaces (the p-port, the s-port, and the u-port) to connect to one another independently. with this architecture, using antioch? to connect a device to a pc through an usb does not dist urb the functions of the device. it still accesses mass storage at the same time the pc is synchronizing with the main processor. the slim architecture enables new usage models, in which a pc accesses a mass storage device independent of the main processor, or enumerates access to both the mass storage and the main processor at the same time. in a handset, this typically enables the user to use the phone as a thumb drive or download media files to the phone while still having full functionality available on the phone. the same phone even functions as a modem to connect the pc to the web. turbo-mtp support turbo-mtp is an implementation of microsoft?s media transfer protocol (mtp) enabled by west bridge ? antioch?. in the current generation of mtp-enabled mobile phones, all protocol packets need to be handled by the main processor. west bridge turbo-mtp switches these packet types and sends only control packets to the processor, while data payloads are written directly to mass storage. this brings the high performance of west bridge to mtp. for mo re information on tur bo-mtp, refer to the application note an48864 ?performance optimization by west bridge controllers with turbo-mtp?. 8051 microprocessor the 8051 microprocessor embedded in antioch does basic transaction management for all the transactions between the p-port, the s-port, and the u-port. the 8051 does not reside in the data path; it manages the path. the data path is optimized for performance. the 8051 exec utes firmware that supports nand, sd, and mmc devices at the s-port. for the nand device, the 8051 firmware follows the smart media algorithm to support: physical to logical management ecc correction wear leveling nand flash bad block handling configuration and status registers the west bridge antioch device includes configuration and status registers that are accessible as memory mapped registers through the processor interface. the configuration registers allow the system to specify certai n behavior from antioch. for example, it masks certain stat us registers from raising an interrupt. the status registers convey the status of different parameters of antioch, such as the addresses of buffers for read operations. processor interface (p-port) communication with the external pr ocessor is realized through a dedicated processor interface. this interface supports both synchronous and asynchronous sram mapped memory accesses. this ensures straightforward electrical communications with the processo r that also has other devices connected on a shared memory bus. asynchronous accesses reach a bandwidth of up to 66.7 mbps. synchronous accesses are performed at 33 mhz across 16 bits for up to 66.7 mbps bandwidth. the memory address is decoded to access any of the multiple endpoint buffers inside antioch. these endpoints serve as buffers for data between each pair of ports, for example, between the processor port and the usb port. the processor writes and reads into these buffers through the memory interface. access to these buffers is cont rolled by using either a dma protocol or an interrupt to the main processor. these two modes are configured by the external processor. as a dma slave, antioch generates a dma request signal to signify to the main processor that it is ready to read from or write to a specific buffer. the external processor monitors this signal and polls antioch for the specific buffers ready for read or write. it then performs the appropriate read or write operations on the buffer through the processor interface. this way, the external processor only deals with the buffers to access a multitude of storage devices conn ected to antioch. in the interrupt mode, antioc h communicates important buffer status changes to the external processor using an interrupt signal. the external processor then polls antioch for the specific buffers ready for read or write and performs the appropriate read or write operations throug h the processor interface. usb interface (u-port) in accordance with the usb 2.0 specification, antioch operates in full speed usb mode in addition to high speed usb mode. the usb interface consists of the usb transceiver. the usb interface accesses and also is accessed by both the p-port and the s-port. the antioch usb interface supports programmable control/bulk/interrupt/isochronous endpoints. mass storage support (s-port) the s-port is configured in two different modes, either simultaneously supporting an sd/mmc+ port and a x8 nand port or supporting a unique x16 nand access port. the nandcfg ball is used to set the configuration of the s-port as either 16-bit nand or 8-bit nand and sd/mmc. the 16-bit interface is only used when there is no other mass storage device connected to the s-port. note that in the wlcsp option, the s-port is not configurable; it only supports a single sd/mmc+ port with no nand port. antioch also includes two chip enables, nand_ce# and nand_ce2#, that enable to access two different nands alternately.
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 4 of 31 nand port (s-port) antioch, as part of its mass st orage management functions, fully manages a nand device. the embedded 8051 manages the actual reading and writing of the nand along with its required protocols. it performs standard nand management functions such as ecc and wear leveling. slc nand devices are supported on all devices in the antioch family. the write performance for connecting to a single slc nand is up to 9 mbps, while read performance is up to 13 mbps. sd/mmc/ce-ata port (s-port) when antioch is configured through nandcfg to support mmc/sd/ce-ata, this interface supports: the multimediacard system s pecification, mmca technical committee, version 4.1 sd memory card specificat ion - part 1, physical layer specification, sd group, vers ion 1.10, october 15, 2004, and version 2.0, november 9, 2005 ce-ata digital protocol, rev 1.1, 28 september, 2005 and ce-ata host design guidance, rev 1.0, 29 september, 2005 west bridge antioch provides support for 1-bit and 4-bit sd cards: 1-bit, 4-bit, and 8- bit mmc, and mmc+. for the sd, mmc/mmc plus card, this block supports one card for one physical bus interface. antioch supports sd commands including the multisector program command that is handled by the api. compatibility with specific ce-ata hdd is subject to confirmation with drive vendors. clocking antioch allows either to connect a crystal between the xtalin and xtalout balls or connect an external clock at the xtalin ball. the power supply level at the crystal supply xvddq determines whether a crystal or a clock is provided. if xvddq is detected as 1.8 v, antioch assumes that a clock input is provided. this clock input must be a 1.8 v square wave. to connect a crystal, xvddq must be 3.3 v. note that the clock inputs at 3.3 v level are not supported. cywb0124ab supports crystals only at 19.2, 24, and 26 mhz. at 48 mhz, only clock inputs are supported. clock inputs are supported at all frequencies. antioch has an on-chip oscillator circuit that uses an external 19.2/24/26 mhz (150 ppm) crystal with the following characteristics: parallel resonant fundamental mode 1 mw drive level 12 pf (5% tolerance) load capacitors [1] figure 1. capacitor 12 pf 12 pf 24 mhz pll c1 c2 12 pf capacitor values assumes a trace capacitance of 3 pf per side on a four-layer fr4 pca table 1. external clock requirements parameter description specification unit min max pn_100hz input phase noise at 100 hz offset ? ?75 dbc/hz pn_1k input phase noise at 1 khz offset ? ?104 dbc/hz pn_10k input phase noise at 10 khz offset ? ?120 dbc/hz pn_100k input phase noise at 100 khz offset ? ?128 dbc/hz pn_1m input phase noise at 1 mhz offset ? ?130 dbc/hz duty cycle 30 70 % maximum frequency deviation ? 150 ppm overshoot ?3% undershoot ?-3% note 1. specified as typical for 24 mhz frequency. load capacitance varies with crystal vendor spec ifications and frequency used.
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 5 of 31 this on-chip pll multiplies the 19.2/24/26/48 mhz frequency up to 480 mhz, as required by the transceiver/phy. the internal counters divide it down for use as the 8051 clock. the 8051 clock frequency is 48 mhz. the xtalin frequency is independent of the clock/data rate of the 8051 microprocessor or any of the device interfaces (including p-port and s-port). the internal pll applies the proper clock multiply option depending on the input frequency. for applications that use an external clock source to drive xtalin, the xtalout ball is left floating. the external clock is a square wave that conforms to high and low voltage levels mentioned in table 3 on page 12 and the rise and fall time specifications in figure 5 on page 14 . the external clock source also stops high or low and is not toggling to achieve the lowest possible current consumption. the requirements for an external clock source are shown in capacitance on page 14 . power domains antioch has multiple power domains that serve different purposes within the chip. *vddq . this refers to a group of five independent supply domains for the digital i/os. the nominal voltage level on these supplies are 1.8 v, 2.5 v, or 3.3 v. specifically, the four separate i/o power domains are: pvddq ? p-port processor interface i/o snvddq ? s-port nand interface i/o ssvddq ? s-port sd interface i/o gvddq ? other miscellaneous i/o uvddq . this is the 3.3 v nominal supply for the usb i/o and some analog circuits. it also supplies power to the usb transceiver. vdd33 . this supply is required for the power sequence control circuits. for more information, see table 2 on page 7 . v dd . this is the supply voltage for the logic core. the nominal supply voltage level is 1.8 v. this supplies the core logic circuits. the same supply is also used for avddq. avddq . this is the 1.8 v supply for pll and usb serializer analog components. the same supply is also used for v dd . maximum permitted noise on avddq is 20 mv p-p. xvddq . this is the clock i/o supply. 3.3 v for xtal or 1.8 v for an external clock. figure 2. antioch power supply domains noise guideline for all supplies except avddq is a maximum of 100 mv p-p. all i/o supplies of antioch are on when a system is active, even if antioch is not used. the core v dd is also deactivated at any time to preser ve power, provided that there is a minimum impedance of 1 k ? between the v dd ball and ground. all i/os tri-state when the core is disabled. power supply sequence the power supplies are independently sequenced without damaging the part. all power supplies are up and stable before the device operates. if all supplies are not stable, the remaining domains are in low power (standby) mode. flexible i/os each of antioch?s ports operate between 1.8 v and 3.3 v with adjustable slew rate for each port and adjustable drive strength for each port for the i/os. the slew rate and drive strength are controlled by registers. power modes in addition to the normal operating mode, antioch contains several low power modes when normal operation is not required. normal mode in this mode, antioch is fully func tional. this is the mode in which the data transfer functions described in this datasheet are performed. suspend mode this mode is entered internally by 8051 (external processor only initiates entry into this mode through mailbox commands). this mode is exited by the d+ bus going low, gpio[0] going to a predetermined state, or by asserting ce# low. in suspend mode of antioch: the clocks are shut off. all i/os maintain their previous state. core power supply are retained. the states of the configuration registers, endpoint buffers, and the program ram are maintained. all transactions are completed before antioch enters suspend mode (state of outstanding transactions are not preserved). the firmware resumes its operation from where it has suspended, because the program counter is not reset. the only inputs that are sensed are reset#, gpio[0], d+, and ce#. the last three are wakeup sources (each is individually enabled or disabled). hard reset is performed by asserting the reset# input and antioch performs initialization. usb-io d-core i/o uvddq vdd d+ d- *vddq
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 6 of 31 standby mode standby mode is a low power state. this is the lowest power mode of antioch while still maintaining external supply levels. this mode is entered through the deassertion of the wakeup input ball or through internal register settings. it is exited by asserting the wakeup ball if the mode is entered by deasserting the wakeup ball. exiting standby mode is also accomplished by asserting ce# low or processor writes to internal registers. in this mode, the following characteristics apply: all configuration register sett ings and program ram contents are preserved. however, data in the buffers or other parts of the data path, if any, is not guaranteed in values. therefore, the external processor ensures that the required data is read before antioch is moved into this standby mode. ? the program counter is reset upon waking up from standby mode. ? all outputs are tri-stated (except uvalid), and i/o is placed in input only configuration. va lues of i/os in standby mode are listed in the table 2 on page 7 . ? core power supply is retained. ? hard reset is performed by a sserting the reset# input, and antioch performs initialization. ? pll is disabled. core power down mode the core power supply v dd is powered down in this mode. avddq is tied to the same supply as v dd and as a result, is also powered down. the endpoint buffers, configuration registers, and the program ram do not mainta in state. it is necessary to reload the firmware upon exiting from this mode. it is required that all vddq power supplies (except avddq) are on and not powered down in this mode. vdd33 must remain on and the requirement of a minimum impedance of 1 k ? between the v dd ball and ground remains unchanged. in the wlcsp option, avddq is internally tied to xvddq. as a result, the clock input at xtalin must be brought to a steady low level before entry into core power down mode. antioch in wlcsp antioch is available in a wafer level chip scale package (wlcsp) with 81 balls. the wlcsp differs from the vfbga in the following ways: the xtalin input only accepts clock inputs and no crystals. the xtalout ball and the xvddq power domain do not exist in this package. the xvddq power domain is internally combined with avddq. since avddq and as a result, xvddq, are off in the core power down mode, the clock input at xtalin must be brought to a steady low level before entry into core power down mode. nand functionality is not avai lable. snvddq does not exist as a separate power domain. it is internally combined with ssvddq. the p-port clk ball and the p-port synchronous mode operation are not available. the p-port is operated only in asynchronous mode. gvddq is not a separate power domain in the wlcsp package. it is internally combined with pvddq. availability of specific signals on the wlcsp option is detailed in table 2 on page 7 .
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 7 of 31 the ball assignment table for cywb0124ab, cywb0125ab follows. table 2. ball assignment [2, 3, 4] vfbga wlcsp ball name i/o ball description standby reset [5] power domain p port j2 n/a clk i clock for p-port - - pvddq vgnd g1 g8 ce# i chip select for p-port. active low - - h3 j6 a[7] i bit 7 of address bus for p-port - - h2 j7 a[6] i bit 6 of address bus for p-port - - h1 j8 a[5] i bit 5 of address bus for p-port - - j3 h6 a[4] i bit 4 of address bus for p-port - - j1 h7 a[3] i bit 3 of address bus for p-port - - k3 j9 a[2] i bit 2 of address bus for p-port - - k2 h8 a[1] i bit 1 of address bus for p-port - - k1 h9 a[0] i bit 0 of address bus for p-port - - g2 g9 dq[15] i/o bit 15 of data bus for p-port z z g3 g7 dq[14] i/o bit 14 of data bus for p-port z z f1 f8 dq[13] i/o bit 13 of data bus for p-port z z f2 f9 dq[12] i/o bit 12 of data bus for p-port z z f3 f7 dq[11] i/o bit 11 of data bus for p-port z z e1 e9 dq[10] i/o bit 10 of data bus for p-port z z e2 e8 dq[9] i/o bit 9 of data bus for p-port z z e3 e7 dq[8] i/o bit 8 of data bus for p-port z z d1 d9 dq[7] i/o bit 7 of data bus for p-port z z d2 d8 dq[6] i/o bit 6 of data bus for p-port z z d3 d7 dq[5] i/o bit 5 of data bus for p-port z z c1 c9 dq[4] i/o bit 4 of data bus for p-port z z c2 c8 dq[3] i/o bit 3 of data bus for p-port z z c3 c7 dq[2] i/o bit 2 of data bus for p-port z z b1 b9 dq[1] i/o bit 1 of data bus for p-port z z b2 b8 dq[0] i/o bit 0 of data bus for p-port z z a1 a9 adv# i address valid for p-port. valid during asynchronous mode. adv# deassertion causes to latch the address. -- b3 a8 oe# i output enable. controls the data bus output drive. ignored during write cycle. active low. -- a2 b7 we# i write enable. signals a read (high) or write (low) access cycle. -- a3 a7 int# o interrupt request. assertion indicates that an interrupt event has occurred. active low. zz a4 c6 drq# o dma request. assertion indicates to processor that it is ready to read or write one or more endpoints. it reflects register cy_an_mem_p0_drq epndrq assertions. active low or high (programmable). zz b4 c5 dack# i dma acknowledgement. assertion indicates dma acknowledgement from processor. is configured in ack mode (asserted throughout dma transfer) or eob mode (pulsed at end of dma transfer). active low or high (program- mable). -- notes 2. unused inputs: must be connected to high/v dd or low/gnd (negligible difference in current drawn) logic level, through a single 10 k pull-up resistor. the only exceptions are wakeup, nandcfg and clk. wa keup is tied high for normal operation a nd nandcfg is tied low for unused nand with s d or tied high for 16-bit nand with no sd. clk is tied low for asynchronous p-port operation. 3. unused i/os: for lowest leakage, unused i/os must be connected to a high logic level. it is recommended that connection to th e power supply is through a single 10k ohm pull-up resistor for all unused i/os. 4. no antioch balls have internal pull-up or pull-down resistors. input/output balls may require external pull-up or pull-down r esistors depending on the application. the pull-up resistors used to indicate speed capability on the usb are included in antioch and need not be connected externally. 5. the reset column indicates the state of signals during reset (reset# asserted). the standby column indicates signal state dur ing standby (low power operating mode through wakeup deassertion) or core v dd deactivation.
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 8 of 31 s port sd and 8-bit nand configuration 16-bit nand configuration g9 h2 sd_d[7] nand_io[15] i/o serve as sd_d[7] for sd port or nand_io[15] for nand upper i/o port depending on nandcfg selection. nand configuration is not available in wlcsp. zz ssvddq vgnd g10 h1 sd_d[6] nand_io[14] i/o serve as sd_d [6] for sd port or nand_io[14] for nand upper i/o port depending on nandcfg selection. nand configuration is not available in wlcsp. zz f9 g3 sd_d[5] nand_io[13] i/o serve as sd_d[5] for sd port or nand_io[13] for nand upper i/o port depending on nandcfg selection. nand configuration is not available in wlcsp. zz f10 g2 sd_d[4] nand_io[12] i/o serve as sd_d [4] for sd port or nand_io[12] for nand upper i/o port depending on nandcfg selection. nand configuration is not available in wlcsp. zz e9 f2 sd_d[3] nand_io[11] i/o serve as sd_d[3] for sd port or nand_io[11] for nand upper i/o port depending on nandcfg selection. nand configuration is not available in wlcsp. zz e10 e3 sd_d[2] nand_io[10] i/o serve as sd_d [2] for sd port or nand_io[10] for nand upper i/o port depending on nandcfg selection. nand configuration is not available in wlcsp. zz d9 e2 sd_d[1] nand_io[9] i/o serve as sd_d[1] for sd port or nand_io[9] for nand upper i/o port depending on nandcfg selection. nand configuration is not available in wlcsp. zz d10 e1 sd_d[0] nand_io[8] i/o serve as sd_d[0] for sd port or nand_io[8] for nand upper i/o port depending on nandcfg selection. nand configuration is not available in wlcsp. zz f8 g1 sd_clk n/a o clock output for the sd interface. frequency is changed and clock is disabled through firmware control. zz g8 h3 sd_cmd n/a i/o sd command/response ball. z z h8 g4 sd_pow n/a o sd power control. this gpio is used to control sd/mmc card power fet if present. high indicates on, low indicates off. zz h10 d1 sd_wp n/a i sd write protection detection. connected to gpio for firmware detection. high indicates that the device connected to the sd port has write protect enabled. -- k7 n/a nand_io[7] nand_io[7] i/o nand_io[7] for nand upper i/o port z z snvddq vgnd k8 n/a nand_io[6] nand_io[6] i/o nand_io[6] for nand upper i/o port j8 n/a nand_io[5] nand_io[5] i/o nand_io[5] for nand upper i/o port k9 n/a nand_io[4] nand_io[4] i/o nand_io[4] for nand upper i/o port j9 n/a nand_io[3] nand_io[3] i/o nand_io[3] for nand upper i/o port h9 n/a nand_io[2] nand_io[2] i/o nand _io[2] for nand upper i/o port k10 n/a nand_io[1] nand_io[1] i/o nand_io[1] for nand upper i/o port j10 n/a nand_io[0] nand_io[0] i/o nand_io[0] for nand upper i/o port k6 n/a nand_cle nand_cle o nand command latch enable [6] zz j6 n/a nand_ale nand_ale o nand address latch enable [6] zz j5 n/a nand_ce# nand_ce# o nand chip enable. active low. [6] zz k4 n/a nand_re# nand_re# o nand read enable. active low. z z h6 n/a nand_we# nand_we# o nand write enable. active low. z z j7 n/a nand_wp# nand_wp# o nand write protect. active low. [6] zz j4 n/a nand_r/b# nand_r/b# i nand ready/bu sy. nand output is open drain. active low. -- k5 n/a nand_ce2# nand_ce2# o nand chip enable 2. allows to access the second nand device. active low. [6] zz table 2. ball assignment [2, 3, 4] (continued) vfbga wlcsp ball name i/o ball description standby reset [5] power domain note 6. the nand_ce#, nand_ce2#,nand_wp#, nand_cle, and nand_ale pins are used as general purpose outputs if nand functionality is no t used.
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 9 of 31 u-port a5 a4 d+ i/o/z usb d+ z z uvddq uvssq a6 a5 d? i/o/z usb d? z z a7 b4 uvalid o external usb switch control. reflects value of register cy_an_mem_pmu_update.uvalid. low low others a8 a2 xtalin i input for either crystal or clock signal. xvddq is 3.3 v for crystal input; xvddq is 1.8 v for clock input. -- xvddq vgnd b8 n/a xtalout [7] o output to connect to feedback input of crystal. is left floating when external clock at xtalin. zz c10 c2 reset# i reset. asserted to place antioch into reset mode and subsequent initialization. active low. -- gvddq vgnd b10 n/a resetout o reset out. deasserted low when reset# is asserted low. asserted high after reset# is deasserted and initialization is complete. reflects value of rstcmpt bit. zlow c9 d3 gpio[1] i/o general purpose input/output. z z d8 d2 gpio[0] i/o general purpose input/output.gpio[0] is used for sd card detect with firmware detection. low indicates card is inserted. zz c7 c1 wakeup [8] i wake up signal. 1 = normal operation, 0 = low power ?sleep? mode. is asserted for antioch to initialize. -- config c5 c3 xtalslc[1] i clock select. for cywb0124ab, xtalslc[1:0] is decoded as: 00 = 19.2 mhz, 01 = 24 mhz, 10 = 48 mhz, 11 = 26 mhz. -- c4 c4 xtalslc[0] i clock select. for cywb0124ab, xtalslc[1:0] is decoded as: 00 = 19.2 mhz, 01 = 24 mhz, 10 = 48 mhz, 11 = 26 mhz. -- c6 n/a nandcfg i s-port configuration. ?0? selects 8-bit nand and sd/mmc configuration. ?1? selects 16-bit nand configuration. -- e8 b1 test[2] i test mode selection. is tied to vgnd for normal operation (cmos level inputs). -- c8 d4 test[1] i test mode selection. is tied to vgnd for normal operation (cmos level inputs). -- d7 a1 test[0] i test mode selection. is tied to vgnd for normal operation (cmos level inputs). -- power d4, h4 e5, a6 pvddq power power for p-port i/o. 1.8 v, 2.5 v, or 3.3 v nominal. - - h5 n/a snvddq power power for nand port i/o. 1.8 v, 2.5 v, or 3.3 v nominal. -- b5 b5 uvddq power power for usb i/o. 3.3 v nominal. - - h7 f1, f3, f4, g5, h4, h5, j2, j3, j4, j5 ssvddq power power for sd port, is connected to snvddq if using 16-bit nand. 1.8 v, 2.5 v, or 3.3 v nominal. -- d6 n/a gvddq power power for miscellaneous i/o. 1.8 v, 2.5 v, or 3.3 v nominal. -- b9 b3 avddq power power for internal pll and usb serializer. 1.8 v nominal. -- b7 n/a xvddq power power for crystal or clock i/o. 1.8 v (clock) or 3.3 v (crystal) nominal. -- d5, g4, g5, g6, g7, f7 d6, f6, g6, j1 v dd power power for core. 1.8 v nominal. - - a10 n/a vdd33 [9] power power sequence control supply. 3.3 v nominal. - - b6 a3 uvssq power ground for all usb. - - a9 b2 avssq power ground for pll. - - e4, e5, e6, e7, f4, f5, f6 b6, d5, e4, e6, f5 vgnd power ground for core. - - table 2. ball assignment [2, 3, 4] (continued) vfbga wlcsp ball name i/o ball description standby reset [5] power domain notes 7. xtalout is driven high during standby mode. xtalout operates the same during reset# assertion and normal mode: fixed high whe n xvddq is 1.8 v (ext clock) and actively toggles w hen xvddq is 3.3 v (crystal). 8. when reset# is asserted, the device enters reset state and wakeup is ignored. 9. vdd33: in cywb0124ab, the ball is no-connect internally. it han dles power sequence control in future west bridge products. wh en migrating to astoria, it is connected to the highest supply to the device. if u sb is used, for example, then vdd33 is connec ted to nominal 3.3 v (because 3.3 v is re quired for usb). vdd33 is always supplied in astoria.
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 10 of 31 figure 3. cywb0124ab 100-ball vfbga ? top view 12345678910 a adv# we# int# drq# d+ d- uvalid xtalin avssq vdd33 a b dq[1] dq[0] oe# dack# uvddq uvssq xvddq xtalout avddq resetout b c dq[4] dq[3] dq[2] xtalslc[0] xtalslc[1] nandcfg wakeup test[1] gpio[1] reset# c d dq[7] dq[6] dq[5] pvddq vdd gvddq test[0] gpio[0] sd_d[1] sd_d[0] d e dq[10] dq[9] dq[8] vgnd vgnd vgnd vgnd test[2] sd_d[3] sd_d[2] e f dq[13] dq[12] dq[11] vgnd vgnd vgnd vdd sd_clk sd_d[5] sd_d[4] f g ce# dq[15] dq[14] vdd vdd vdd vdd sd_cmd sd_d[7] sd_d[6] g h a[5] a[6] a[7] pvddq snvddq nand_we# ssvddq sd_pow nand_io[2] sd_wp h j a[3] clk a[4] nand_r/b# nand_ce# nand_ale nand_wp# nand_io[5] nand_io[3] nand_io[0] j k a[0] a[1] a[2] nand_re# nand_ce2# nand_cle nand_io[7] nand_io[6] nand_io[4] nand_io[1] k 12345678910 top view uvddq gvddq ssvddq vgnd pvddq snvddq power domain key
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 11 of 31 figure 4. cywb0124ab 81-ball wlcsp ? top view uvddq avddq, vdd ssvddq v gnd pvddq power domain key 1 23456789 a test[0] xtalin uvssq d+ d- pvddq int# oe# adv# a b test[2] avssq avddq uvalid uvddq vgnd we# dq[0] dq[1] b c wakeup reset# xtalslc[1] xtalslc[0] dack# drq# dq[2] dq[3] dq[4] c d sd_wp gpio[0] gpio[1] test[1] vgnd vdd dq[5] dq[6] dq[7] d e sd_d[0] sd_d[1] sd_d[2] vgnd pvddq vgnd dq[8] dq[9] dq[10] e f ssvddq sd_d[3] ssvddq ssvddq vgnd vdd dq[11] dq[13] dq[12] f g sd_clk sd_d[4] sd_d[5] sd_pow ssvddq vdd dq[14] ce# dq[15] g h sd_d[6] sd_d[7] sd_cmd ssvddq ssvddq a[4] a[3] a[1] a[0] h j vdd ssvddq ssvddq ssvddq ssvddq a[7] a[6] a[5] a[2] j 123456789
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 12 of 31 absolute maximum ratings operating range specifies temperature and voltage boundary conditions for safe operation of the device. operation outside these boundaries may affect t he performance and life of the device. these user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power supplied (industri al) ........................ ?40 c to +85 c supply voltage to ground potential v dd , avddq ................................................?0.5 v to +2.0 v gvddq, pvddq, ssvddq, snvddq, uvddq and vdd33 and xvddq ...............?0.5 v to +4.0 v dc input voltage to any input ball ........... .......1.89 v to 3.6 v (depends on i/o supply voltage. inputs are not over voltage tolerant.) dc voltage applied to outputs in high z state ........... .......... ?0.5 v to vddq+0.5 v static discharge voltage (esd) from jesd22-a114 ................................................. > 2000 v latch-up current .................................................... > 200 ma maximum output short circuit current for all i/o configurations. (v out = 0 v) [10] .............. ?100 ma operating conditions t a (ambient temperature under bias) industrial .................................................... ?40 c to +85 c v dd , av ddq supply voltage .............................1.7 v to 1.9 v uv ddq supply voltage .....................................3.0 v to 3.6 v pv ddq , gv ddq , snv ddq , ssv ddq supply voltage ..................................................1.7 v to 3.6 v xvddq (crystal i/o) supply voltage ...............3.0 v to 3.6 v xvddq (ext. clock i/o) supply vo ltage ...........1.7 v to 1.9 v dc characteristics table 3. dc specifications for all voltage supplies parameter description conditions min typ max unit v dd core voltage supply 1.7 1.8 1.9 v avddq analog voltage supply 1.7 1.8 1.9 v xvddq crystal voltage supply 3.0 3.3 3.6 v xvddq clock voltage supply 1.7 1.8 1.9 v pvddq [11] processor interface i/o 1.7 1.8, 2.5, 3.3 3.6 v gvddq [11] miscellaneous i/o voltage supply 1.7 1.8, 2.5, 3.3 3.6 v snvddq [11] s-port nand i/o voltage supply 1.7 1.8, 2.5, 3.3 3.6 v ssvddq [11, 12] s-port sd i/o voltage supply 1.7 1.8, 2.5, 3.3 3.6 v uvddq [13] usb voltage supply 3.0 3.3 3.6 v vdd33 power sequence control supply 3.0 3.3 3.6 v v ih1 [14] input high voltage 1 all ports except usb, 2.0 v ? v cc ? 3.6 v 0.625 v cc ?v cc + 0.3 v v ih2 [14] input high voltage 2 all ports except usb, 1.7 v ? v cc < 2.0 v v cc ? 0.4 ? v cc + 0.3 v il input low voltage ?0.3 ? 0.25 v cc v v oh output high voltage i oh (max) = ?0.1 ma 0.9 v cc ??v v ol output low voltage i ol (min) = 0.1 ma ? ? 0.1 v cc v i ix input leakage current all i/o signals held at vddq ?1 ? 1 ? a i oz output leakage current all i/o signals held at vddq ?1 ? 1 ? a i cc core operating current of core voltage supply (v dd ) and analog voltage supply (avddq) outputs tri-stated vfbga ? ? 110 ma wlcsp ? ? 115 notes 10. do not test more than one output at a time. duration of the short circuit does not exceed 1 second. tested initially, and af ter any redesign or process changes, may affect these parameters. 11. interfaces with a voltage range are adjustable with respect to the i/o voltage and thus support multiple i/o voltages. 12. the ssvddq i/o voltage is dynamically c hanged (for example, from high range to low range) as long as the supply voltage unde rshoot does not surpass the lower minimum voltage limit. ssvddq levels for sd modes: 2.0 v?3.6 v, mmc modes: 1.7 v?3.6 v. 13. when u-port is in a disabled state, uvddq goes down to 2.4 v, provided uvddq is still the highest supply voltage level. 14. v cc = pertinent v ddq value.
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 13 of 31 i cc crystal operating current of crystal voltage supply (xvddq) [15] xtalout floating vfbga ? ? 5 ma wlcsp ? ? n/a i cc usb operating current of usb voltage supply (uvddq) [15] operating and terminated for high speed mode ??25ma i sb1 total standby current of antioch when device is in suspend mode 1. *vddq = 3.3 v nominal (3.0?3.6 v) 2. outputs and bidirs high or floating [16] 3. xtalout floating 4. d+ floating (no current drawn through internal 1.5 kohm pull-up), d? grounded, uvalid driven low 5. device in suspend mode ? 250 [17] 2500 ? a i sb2 total standby current of antioch when device is in standby mode 1. *vddq = 3.3 v nominal (3.0?3.6 v) 2. outputs and bidirs high or floating [16] 3. xtalout floating 4. d+ floating, d? grounded, uvalid driven low 25 c ? ? 45 ? a 85 c ? ? 290 i sb3 total standby current of antioch when device is in core power down mode 1. outputs and bidirs high or floating [16] 2. xtalout floating 3. d+ floating, d? grounded, uvalid driven low 4. core powered down 25 c ? ? 25 ? a ??139 85 c table 3. dc specifications for all voltage supplies (continued) parameter description conditions min typ max unit notes 15. active current conditions: -uvddq: usb transmitting 50% of the time, receiving 50% of the time. -pvddq/snvddq/ssvddq/gvddq: active current depe nds on i/o activity, bus load, and supply level. -xvddq: assume highest frequency clock (48 mhz) or crystal (26 mhz). 16. the outputs/bidirs that are forced low in standby mode increases i/o supply standby cu rrent beyond specified value. 17. isb1 typical value is not a maximum specification but a ty pical value. isb1 maximum current value specified for 85 c.
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 14 of 31 usb transceiver usb 2.0 compliant in full speed and high speed modes. capacitance parameter description conditions typ max unit c in input ball capacitance, except d+/d? t a = 25 c, f = 1 mhz, v cc = v ccio ?9pf input ball capacitance, d+/d? ? 15 c out output ball capacitance ? 10 pf ac test loads and waveforms figure 5. ac test loads and waveforms
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 15 of 31 ac characteristics usb transceiver usb 2.0 compliant in full speed and high speed modes. p-port interface asynchronous mode timing parameters table 4. asynchronous mode timing parameters parameter description min max unit read timing parameters taa address to data valid ? 30 ns toh data output hold from address change 3 ? ns tea chip enable to data valid ? 30 ns taadv adv# to data valid access time ? 30 ns tavs address valid to adv# high 5 ? ns tavh adv# high to address hold 2 [18] ? ns tcvs ce# low setup time to adv# high 5 ? ns tvph adv# high time 15 [19] ? ns tvp adv# pulse width low 7.5 ? ns toe oe# low to data valid ? 22.5 ns tolz oe# low to low z 3 ? ns tohz oe# high to high z 0 22.5 ns tlz ce# low to low z 3 ? ns thz ce# high to high z ? 22.5 ns write timing parameters tcw ce# low to write end 30 ? ns taw address valid to write end 30 ? ns tas address setup to write start 0 ? ns tadvs adv# setup to write start 0 ? ns twp we# pulse width 22 ? ns twph we# high time 10 ? ns tcph ce# high time 10 ? ns tavs address valid to adv# high 5 ? ns tavh adv# high to address hold 2 [18] ? ns tcvs ce# low setup time to adv# high 5 ? ns tvph adv# high time 15 [19] ? ns tvp adv# pulse width low 7.5 ? ns tvs adv# low to end of write 30 ? ns tdw data setup to write end 18 ? ns tdh data hold from write end 0 ? ns twhz we# low to dq high z output ? 22.5 ns twlz we# high to dq low z output 3 ? ns notes 18. in applications where back-to-back accesses are not performed on different endpoint addresses, the minimum t avh specification is relaxed to 0 ns. 19. in applications where access cycle time is at least 60 ns, t vph is relaxed to 12 ns.
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 16 of 31 figure 6. asynchronous single read timing a adv# ce# oe# we# dq taa tea toe tolz tohz tlz thz valid address high-z tvph tavs tavh tvp valid output taadv figure 7. asynchronous back-to-back read timing a adv# ce# oe# we# dq taa tea tohz tlz thz high-z tvph tavs tavh tvp taadv valid address valid address valid output valid output toh
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 17 of 31 figure 8. asynchronous back-to-back write timing a adv# ce# oe# we# dq_in high-z tvph tavs tavh tvp valid address valid input valid input tdw tdh dq_out tvs tas twhz tlz valid address taw tcw tow twph twp tadvs figure 9. asynchronous read to write timing a adv# ce# oe# we# dq_in high-z tvph tavs tavh tvp valid address valid input valid input tdw tdh dq_out tvs tas twhz valid address taw tow twp taa toe tolz tlz high-z tvph tavs tavh tvp taadv valid address valid output tohz tea
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 18 of 31 synchronous mode timing parameters figure 10. asynchronous write to read timing table 5. synchronous mode timing parameters parameter description conditions min max unit freq interface clock frequency ? 33 mhz tclk clock period 30 ? ns tclkh clock high time 12 ? ns tclkl clock low time 12 ? ns ts ce#/we#/addr/dq setup time 7.5 ? ns th ce#/we#/addr/dq hold time 1.5 ? ns tco clock to valid data ? 18 ns toh clock to data hold time 2 ? ns thz oe# high to data high z ? 22.5 ns tlz oe# low to data low z 3 ? ns toe oe# low to data valid ? 22.5 ns twhz we# low to dq high z output ? 22.5 ns twlz we# high to dq low z output 3 ? ns tckhz clock to data high z ( figure 14 on page 20 ) measured from the rising edge of the second clock after the deassertion of ce# is latched by the rising edge of the clock. ? 18 ns tcklz clock to data low z ( figure 16 on page 22 ) 3 ? ns a adv# ce# oe# we# dq_in tavs tavh tvp valid address valid input tdw tdh dq_out tvs tas twhz taw twp taa toe tolz tavs tavh tvp taadv valid address valid output
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 19 of 31 figure 11. synchronous write timing a[7:0] ce# clk oe# ts th tclk dq[15:0] (input) we# tclkh tclkl an an+1 an+2 an+3 dq[15:0] (output) dn dn+1 dn+2 dn+3 high-z note: - assumes previous cycle had ce# deselected - oe# is don?t care during write operations figure 12. synchronous read timing a[7:0] ce# clk oe# ts th tclk dq[15:0] (input) we# tclkh tclkl an an+1 an+2 an+3 dq[15:0] (output) dn dn+1 high-z note: - assumes previous cycle had ce# deselected an+4 high-z toh tco thz tlz toe
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 20 of 31 figure 13. synchronous read (oe# fixed low) timing a[7:0] ce# clk oe# ts th we# ax ax+1 dq[15:0] (output) note: - assumes previous several cycles were read toh dx-1 dx-2 tco dx tckhz ax+2 dx dx+1 figure 14. synchronous read to write (oe# controlled) timing a[7:0] ce# clk oe# ts th tclk dq[15:0] (input) we# tclkh tclkl ax ax+1 an an+1 dq[15:0] (output) high-z note: - assumes previous several cycles were read - (ax) and (ax+1) cycles are turnaround. (ax+1) operation does not cross pipeline. an+2 toh dn dn+1 thz dx-1 dx-2 tco ts th dn+2 dx
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 21 of 31 figure 15. synchronous read to write (oe# fixed low) timing a[7:0] ce# clk oe# ts th tclk dq[15:0] (input) we# tclkh tclkl ax ax+1 ax+2 an dq[15:0] (output) high-z note: - assumes previous several cycles were read - in this scenario, oe# is held low - (ax) and (ax+1) cycles are turnaround. (ax+1) operation does not cross pipeline. - no operation is performed during the ax+2 cycle (true turnaround operation) an+1 toh dn dn+1 dx-1 dx-2 tco ts th tco dx twhz
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 22 of 31 figure 16. synchronous write to read timing a[7:0] ce# clk oe# ts th tclk dq[15:0] (input) we# tclkh tclkl an an+1 an+2 an+3 dq[15:0] (output) high-z note: - assumes previous cycle has ce# deselected - in this scenario, oe# is held low an+4 dn dn+1 ts th dn+2 toh tco tcklz twlz
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 23 of 31 sd/mmc parameters figure 17. sd/mmc timing waveform - all modes sd_cmd/ sd_d0-d3 output sd_clk tsdclk tsdclkl sd_cmd/ sd_d0-d3 input tsdclkh tsdoh tsdos tsdih tsdis tsdckhz tsdcklz table 6. common timing parameters for sd and mmc ? during identification mode parameter description min max unit sdfreq sd_clk interface clock frequency ? 400 khz tsdclk clock period 2.5 ? ? s tsdclkh clock high time 1.0 ? ? s tsdclkl clock low time 1.0 ? ? s table 7. common timing parameters for sd and mmc ? during data transfer mode parameter description min max unit sdfreq sd_clk interface clock frequency 5 48 mhz tsdclk clock period 20.8 200 ns tsdclkod clock duty cycle 40 60 % tsclkr clock rise time ? 3 ns tsclkf clock fall time ? 3 ns table 8. timing parameters for sd ? all modes parameter description min max unit tsdis input setup time 4 ? ns tsdih input hold time 2.5 ? ns tsdos output setup time 7 ? ns tsdoh output hold time 6 ? ns tsdckhz clock to data high z ? 18 ns tsdcklz clock to data low z 3 ? ns table 9. timing parameters for mmc ? all modes parameter description min max unit tsdis input setup time 4 ? ns tsdih input hold time 4 ? ns tsdos output setup time 6 ? ns tsdoh output hold time 6 ? ns tsdckhz clock to data high z ? 18 ns tsdcklz clock to data low z 3 ? ns
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 24 of 31 reset and standby timing parameters figure 18. reset and standby timing diagram reset# resetout wakeup uvalid firmware init complete mandatory reset pulse standby mode hard reset high-z firm ware init complete usb switch enabled usb switch disabled mandatory reset pulse firmware init complete cy_an_mem_pmu_update.uvalid bit is set to ?1? cy_an_mem_pmu_update.uvalid bit is set to ?0? cy_an_mem_pmu_update.uvalid bit is set to ?0? tslp trpw tw pw vdd (core) core power-down vddq (i/o) xtalin xtalin up & stable before wakeup asserted tw h trh trr tw u table 10. reset and standby timing parameters parameter description conditions min max unit tslp sleep time ? 1 ms twu wakeup time from standby mode clock on xtalin 1 ? ms crystal on xtalin-xtalout 5 ? ms twh wakeup high time 5 ? ms twpw wakeup pulse width 5 ? ms trh reset# high time 5 ? ms trpw reset# pulse width clock on xtalin 1 ? ms crystal on xtalin-xtalout 5 ? ms trr reset# recovery time 1 ? ms
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 25 of 31 ordering information ta b l e 11 lists the key package features and ordering codes. the table contains only the parts that are currently available. if you do not see what you are looking for, contact your local sales repr esentative. for more information, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products . ordering code definitions table 11. key features and ordering information ordering code turbo-mtp enabled package type available clock input frequencies (mhz) cywb0124ab-bvxi no 100 vfbga ? pb-free 19.2, 24, 26, 48 cywb0124abx-fdxi no 81 wlcsp ? pb-free 19.2, 24, 26, 48 cywb0125abx-fdxi yes 81 wlcsp ? pb-free 19.2, 24, 26, 48 cy family: west bridge wb 012 4, 5 antioch bridge company id: cy = cypress ab turbo mtp is enabled 4 = no, 5 = yes a generation x bga, csp bv, fd bv = vfbga, fd = wlcsp x pb-free i temperature: industrial
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 26 of 31 package diagrams figure 19. 100 vfbga (6 6 1.0 mm) bz100a figure 20. 81 wlcsp (3.784 3.788 0.55 mm) 51-85209 *d 001-13820 *f
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 27 of 31 acronyms document conventions units of measure table 12. acronyms used in this document acronym description dc direct current dma direct memory access esd electrostatic discharge ecc error correction codes hdd hard disk drive mtp media transfer protocol mmc multimedia card pll phase-locked loop slim simultaneous link to independent media slc single level cell usb universal serial bus wlcsp wafer level chip scale package ce-ata consumer electronics - advanced technology attachment table 13. units of measure symbol unit of measure a ampere dbc decibels relative to the carrier khz kilohertz mbps megabyte per second mhz megahertz a microampere s microsecond ms millisecond ns nanosecond ppm parts per million pf picofarad v volt ma milliampere
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 28 of 31 document history page document title: cywb0124 ab/cywb0125ab, west bridge ? antioch? usb/mass storage peripheral controller document number: 001-07978 revision ecn orig. of change submission date description of change ** 460480 odc see ecn new release *a 539922 vso see ecn removed all cywb0224ab (this is astoria p/n) removed cywb0224ab additional features removed mlc nand support wordings removed ce-ata specification added 26 mhz for the clock support removed the paragraph of cywb0224ab removed note 1 corrected note 7 is the same as pdd added astoria as a future product in note 9 added reference figures in tckhz and tcklz added condition description to tckhz added figure 11 updated figure 14 removed cywb0224ab-bvxi, removed the columns of ce-ata and mlc nand support *b 567593 vso see ecn minor change: post part cywb0124ab on external website under nda. *c 841760 ruy see ecn page-1, changes to the mass storage support with addition of ce-ata updated the revision numbers of sd card specifications added ce-ata specifications clarified footnote 5 that unused inputs are tied through 10k pull up resistors and that clk is low in asynchronous p-port operation footnote 6, 100k resistor is changed to 10k footnote 7, a sentence on resistors for speed capability on usb is added sdio is changed to sd in pin assignment table in clocking, changed crystal requirement from 50 to 100 ppm. clarified core power down mode that avddq is also powered down. split tas into tas and tadvs and twph into twph and tcph in table 5 updated figure 5 to depict toh updated figure 6 to depict tadvs and corrected tcw updated figure 1 to remove ?access control? added external clock requirements and table 1 added section on flexible i/os specified values in absolute maximum ratings (changed from tbs) in table 3, updated v ih value for supplies other than uvddq, and added pertinent notes 15 and 16. appended to note 12 that maximum current values are measured at 85c. added maximum current values for i sb1, i sb2 and i sb3 in table 5, the following changes are made: toh, tolz, tlz, and tow changed from 5 to 3 ns; tvp changed from 5 to 7.5 ns; toe, tohz, thz, and twhz changed from 20 to 22.5 ns. added notes [17] and [18] in table 6, thz and toe changed form 18 to 22.5 ns.
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 29 of 31 *d 1067820 ruy see ecn added table 10 added ?ssvddq levels for sd modes: 2.0v - 3.6v, mmc modes:1.7v - 3.6v.? to note 11 in table 5 added notation of tsdckhz and tsdcklz to figure 15 added undershoot and overshoot parameters and removed the supply voltage noise requirement in table 1 external clock requirements added representation of twhz to figure 13 and twlz to figure 14 added twhz and twlz to table 5 changed name of parameter tow to twlz in table 6 added ?and less than 4x4 mm wlcsp? to features added figure 19 added wlcsp ordering information added functionality of antioch in wlcsp added figure 3 added two columns to table 1 showing the balls are available in the wlcsp and vfbga packages added ?note that in the wlcsp option, the s-port is not configurable; it only supports a single sd/mmc+ port with no nand port.? to mass storage support section added ?availability of specific signals on the wlcsp option is detailed in pin assignments.? to antioch in wlcsp. added ?maximum permitted noise on avddq is 20 mv p-p.? and ?noise guideline for all supplies except avddq is maximum 100 mv p-p.? to antioch power domains section changed maximum value of isb3 in table 3 from 170 ua to 139 ua. changed ?typical? values for isb2 and isb3 to correct definition of ?maximum? value at 25c. isb1 has typical value at 25c. removed ?these values are based upon simulation and are subject to change p ending closure of full device character- ization.? from note 10 added figure 16 and table 11 changed reference from ?pin? to ?ball? in table 2 and throughout the data sheet. corrected the ball description of sd_wp in table 2 to say that sd_wp being high, not low indicates that the card is write protected added the requirement that xtalin is low before entry into core power down mode in core power down mode and antioch in wlcsp sections re-ordered paragraphs in clocking section added ?the external clock is a square wave that conforms to high and low voltage levels mentioned in table 3 and the rise and fall time specifications? in figure 17 clarified standby mode section to reflect that wakeup assertion releases antioch from standby mode only when the mode is entered by de-asserting wakeup *e 1116363 ruy see ecn changed part number for the wlcsp part from cywb0124ab-fdxi to cywb0124abx-fdxi in orde ring information table updated the information from *b version of specification 001-13820 in the package diagram of wlcsp removed mention of erroneous change in isb1 parameter in *d version from document history table *f 1408263 aesa see ecn changed the dc characteristics to differentia te between icc crystal for antioch vfbga and wlcsp added a footnote to nand_ce#, nand_ce2#, nand_wp#, nand_cle, and nand_ale pins in the pin assignment table. document history page (continued) document title: cywb0124 ab/cywb0125ab, west bridge ? antioch? usb/mass storage peripheral controller document number: 001-07978 revision ecn orig. of change submission date description of change
cywb0124ab cywb0125ab document number: 001-07978 rev. *m page 30 of 31 *g 1489983 osg / aesa see ecn in dc characteristics table, changed icc crystal and icc core to differentiate between values for vfbga and wlcsp in dc characteristics table, clarif ied the isb1 measurement conditions. *h 2572476 osg / aesa 09/25/2008 updated phase noise specifications for input clock - table 1 updated ppm specification to 150 ppm for input clock and crystal - table 1 added turbo-mtp support intro duction to functional overview added turbo-mtp part numbers to ordering information added part number cywb0125ab changed data sheet title to ?cywb0124ab/cywb0125ab west bridge? antioch? usb/mass storage peripheral controller? updated data sheet template *i 2949425 odc 10/22/10 template and styles update. added ordering code definitions. added acronym table and units of measure. included table of contents. updated package diagrams. *j 3201726 aesa 03/21/11 removed pr uned part cywb0125ab-bvxi from ordering information. updated figure 19 on page 26 *k 3553527 aasi 03/16/ 2012 post the datash eet to cypress.com. *l 3847849 hbm 12/20/2012 updated package diagrams : spec 001-13820 ? changed revision from *e to *f. *m 4197479 hbm 11/20/2013 updated in new template. completing sunset review. document history page (continued) document title: cywb0124 ab/cywb0125ab, west bridge ? antioch? usb/mass storage peripheral controller document number: 001-07978 revision ecn orig. of change submission date description of change
document number: 001-07978 rev. *m revised november 20, 2013 page 31 of 31 west bridge is a registered trademark of cypress semiconductor corp. slim and antioch are trademarks of cypress semiconductor c orp. all other trademarks or registered trademarks referenced herein are the property of their respective owners. cywb0124ab cywb0125ab ? cypress semiconductor corporation, 2005-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.com/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cypress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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